This disclosure generally relates to transmitter and receiver systems. In particular, this disclosure relates to systems that facilitate a partial-rate data transfer mode using fixed-clock-rate interfaces.
Present computing and communication systems require progressively higher off-chip communications bandwidth, and multi-Gb/s serial links for chip-to-chip interconnects are becoming ubiquitous. Meanwhile, power consumption is becoming an increasingly important design metric, especially for mobile applications. System designers often face the challenge of providing high bandwidth, low power consumption, and minimal latency at the same time.
TABLE 1 presents a set of exemplary power-consumption values and the amount of time for transitions between different modes in a 6.25 Gb/s system which can operate in a partial-rate transfer mode but configured to operate in conventional modes, in accordance with one embodiment of the present invention.
TABLE 2 presents a set of exemplary power-consumption values and the amount of time for transitions between modes in a 6.25 Gb/s system configured to operate in a partial-rate transfer mode in accordance with one embodiment of the present invention.
In the drawings, the same reference numbers identify identical or substantially similar elements or acts. The most significant digit or digits in a reference number refer to the figure number in which that element is first introduced. For example, element 102 is first introduced in and discussed in conjunction with FIG. 1.